The present invention generally relates to a wafer level package and a method for forming and more particularly, relates to a wafer level package that utilizes elastomeric pads in dummy plugs for forming I/O redistribution and a method for forming such package.
In the fabrication of modern semiconductor devices, the ever increasing device density and decreasing device dimensions demand more stringent requirements in the packaging or interconnecting techniques of such high density devices. Conventionally, a flip-chip attachment method has been used in packaging of semiconductor chips. In the flip-chip attachment method, instead of attaching a semiconductor die to a lead frame in a package, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out in an evaporation method by using a composite material of tin and lead through a mask for producing a desired pattern of solder bumps. The technique of electrodeposition has been more recently developed to produce solder bumps in flip-chip packaging process.
Other techniques that are capable of solder-bumping a variety of substrates to form solder balls have also been proposed. The techniques generally work well in bumping semiconductor substrates that contain solder structures over a minimal size. For instance, one of such widely used techniques is a solder paste screening method which has been used to cover the entire area of an eight inch wafer. However, with recent trend in the miniaturization of device dimensions and the necessary reduction in bump-to-bump spacing (or pitch), the use of the solder paste screening technique has become impractical for several reasons. One of the problems in utilizing solder paste screening technique in bonding modern semiconductor devices is the paste composition itself. A solder paste is formed by a flux material and solder alloy particles. The consistency and uniformity of the solder paste composition become more difficult to control as the solder bump volume decreases. Even though a solution of the problem has been proposed by using solder paste that contain extremely small and uniform solder particles, it can only be achieved at a high cost penalty. A second problem in utilizing the solder paste screening technique in modern high density semiconductor devices is the available space between solder bumps. It is known that a large volume reduction occurs when a solder changes from a paste state to a cured stated, the screen holes for the solder paste must be significantly larger in diameter than the actual solder bumps to be formed. The large volume shrinkage ratio thus makes the solder paste screening technique difficult to carry out in high density devices.
Other techniques for forming solder bumps such as the controlled collapse chip connection (C4) technique and the thin film electrodeposition technique have also been used in recent years in the semiconductor fabrication industry. The C4 technique is generally limited by the resolution achievable by a molybdenum mask which is necessary for the process. Fine-pitched solder bumps are therefore difficult to be fabricated by the C4 technique. Similarly, the thin film electrodeposition technique which also requires a ball limiting metallurgy layer to be deposited and defined by an etching process which has the same limitations as the C4 technique. For instance, a conventional thin film electrodeposition process for depositing solder bumps is shown in FIGS. 1Axcx9c1F.
A conventional semiconductor structure 10 is shown in FIG. 1A. The semiconductor structure 10 is built on a silicon substrate 12 with active devices built therein. A bond pad 14 is formed on a top surface 16 of the substrate 12 for making electrical connections to the outside circuits. The bond pad 14 is normally formed of a conductive metal such as aluminum. The bond pad 14 is passivated by a final passivation layer 20 with a window 22 opened by a photolithography process to allow electrical connection to be made to the bond pad 14. The passivation layer 20 may be formed of any one of various insulating materials such as oxide, nitride or organic materials. The passivation layer 20 is applied on top of the semiconductor device 10 to provide both planarization and physical protection of the circuits formed on the device 10.
Onto the top surface 24 of the passivation layer 20 and the exposed top surface 18 of the bond pad 14, is then deposited an under bump metallurgy layer 26. This is shown in FIG. 1B. The under bump metallurgy (UBM) layer 26 normally consists of an adhesion/diffusion barrier layer 30 and a wetting layer 28. The adhesion/diffusion barrier layer 30 may be formed of Ti, TiN or other metal such as Cr. The wetting layer 28 is normally formed of a Cu layer or a Ni layer. The UBM layer 26 improves bonding between a solder ball to be formed and the top surface 18 of the bond pad 14.
In the next step of the process, as shown in FIG. 1C, a photoresist layer 34 is deposited on top of the UBM layer 26 and then patterned to define a window opening 38 for the solder ball to be subsequently formed. In the following electrodeposition process, a solder ball 40 is electrodeposited into the window opening 38 forming a structure protruded from the top surface 42 of the photoresist layer 34. The use of the photoresist layer 34 must be carefully controlled such that its thickness is in the range between about 30 xcexcm and about 40 xcexcm, preferably at a thickness of about 35 xcexcm. The reason for the tight control on the thickness of the photoresist layer 34 is that, for achieving a fine-pitched solder bump formation, a photoresist layer of a reasonably small thickness must be used such that a high imaging resolution can be achieved. It is known that, during a photolithography process, the thicker the photoresist layer, the poorer is the imaging process. To maintain a reasonable accuracy in the imaging process on the photoresist layer 34, a reasonably thin photoresist layer 34 must be used which results in a mushroom configuration of the solder bump 40 deposited therein. The mushroom configuration of the solder bump 40 contributes greatly to the inability of a conventional process in producing fine-pitched solder bumps.
Referring now to FIG. 1E, wherein the conventional semiconductor structure 10 is shown with the photoresist layer 34 removed in a wet stripping process. The mushroom-shaped solder bump 40 remains while the under bump metallurgy layer 26 is also intact. In the next step of the process, as shown in FIG. 1F, the UBM layer 26 is etched away by using the solder bump 40 as a mask in an wet etching process. The solder bump 40 is then heated in a reflow process to form solder ball 42. The reflow process is conducted at a temperature that is at least the reflow temperature of the solder material.
In recent years, chip scale packages (CSP) have been developed as a new low cost packaging technique for high volume production of IC chips. One of such chip scale packaging techniques has been developed by the Tessera Company for making a so-called micro-BGA package. The micro-BGA package can be utilized in an environment where several of the packages are arranged in close proximity on a circuit board or a substrate much like the arrangement of individual tiles. Major benefits achieved by a micro-BGA package are the combined advantages of a flip chip assembly and a surface mount package. The chip scale packages can be formed in a physical size comparable to that of an IC chip even though, unlike a conventional IC chip such as a flip chip, the chip scale package does not require a special bonding process for forming solder balls. Furthermore, a chip scale package may provide larger number of input/output terminals than that possible from a conventional quad flat package, even though a typical quad flat package is better protected mechanically from the environment.
A unique feature of the chip scale package is the use of an interposer layer that is formed of a flexible, compliant material. The interposer layer provides the capability of absorbing mechanical stresses during the package forming steps and furthermore, allows thermal expansion mismatch between the die and the substrate. The interposer layer, therefore, acts both as a stress buffer and as a thermal expansion buffer. Another unique feature of the chip scale package, i.e. such as a micro-BGA package, is its ability to be assembled to a circuit board by using conventional surface mount technology (SMT) processes.
In a typical micro-BGA package, a flexible interposer layer (which may contain circuit) is used to interconnect bond pads on an IC chip to an array of solder bump connections located on a flexible circuit. The flexible circuit, normally of a thickness of approximately 25 xcexcm, is formed of a polymeric material such as polyimide which is laminated to a silicon elastomer layer of approximately 150 xcexcm thick. The silicon elastomeric layer provides flexibility and compliance in all three directions for relief of stresses and thermal expansion mismatches.
To further reduce the fabrication cost of IC devices, it is desirable that if a whole wafer can be passivated to seal the IC dies on the wafer, and then be severed into individual IC dies from the wafer such that not only the benefits of a chip scale package can be realized, the packaging cost for the IC dies may further be reduced.
A large number of IC chips are designed with a peripheral array of I/O pads. For modern high density devices, the pitch allowed between I/O pads is steadily decreasing. An I/O pad redistribution process is frequently necessary for changing a peripheral array to an area array in order to improve pitch between the conductive pads. During the redistribution process, metal traces are frequently used to extend bond pads from a peripheral area to a center area on the chip. Due to the limited space available for the metal traces, especially those traces that run an extended distance, it is desirable to produce metal traces that are stress buffered in order to assure the reliability of a chip.
In a co-pending application assigned to the common assignee of the present application, Ser. No. 09/274,611, filed Mar. 23, 1999, which is incorporated in its entirety herewith by reference, a method for forming a wafer level package that contains a multiplicity of IC dies each having an I/O redistribution is disclosed. In the method, as depicted in FIG. 2, a wafer level package 44 is formed by first providing a silicon wafer (not shown) which has a multiplicity of IC dies 46 formed on a top surface. Each of the multiplicity of IC dies 46 has at least one first I/O pad 48 formed in a first insulating layer 50. At least one via plug 52 is then formed of a first conductive metal material on top of the at least one first I/O pad 48. A layer of second insulating material 54 that has sufficient elasticity is then coated on the top surface of the IC die 46 leaving a top surface of the at least one via plug 52 substantially exposed from the insulating material layer 54. A second conductive metal layer 56 is then deposited on top of the second insulating material layer 54 to form at least one metal trace 58 with a first end electrically connecting the at least one via plug 52 and a second end extending away from the first end. A third insulating material layer 60 is then deposited on top of the at least one metal trace 58 and is defined to expose at least one second I/O pad at the second end of the at least one metal trace 58. Depositing a UBM (under-bump-metallurgy) layer 62 and forming at least one solder ball 66 on a top surface 64 of the UBM layer 62.
The method shown in FIG. 2, while providing an adequate stress buffer layer 54 for the solder balls 66, requires the step of coating the entire surface of the IC die 46 with an elastomeric material layer, which is time-consuming and costly. A simplified method that is capable of achieving the same desirable stress buffering effect is therefore needed for providing wafer level packages at low cost.
In the wafer level package application depicted in FIG. 2, several processing and performance related problems have been discovered. First, since the elastomeric layer 54 is extensively covered by the polyimide layer 60 in order to provide isolation of the I/O redistribution line 66, and that the elastomeric layer 54 is formed of a material that has high elasticity, the polyimide layer 60 on top frequently forms cracks and becomes deficient in isolating the metal layer 56. A severe reliability problem thus occurs since the metal redistribution lines are no longer isolated by the passivation layer of polyamide. Secondly, the thick elastomeric layer 54 further presents another performance problem for the wafer level package. When the layers under the elastomeric layer 54 is grounded, the elastomeric layer 54 becomes a capacitor with a large capacitance, presenting a problem for the IC device. The wafer level package having the structure shown in FIG. 2 cannot be used when the capacitance of the elastomeric layer becomes an issue.
It is therefore an object of the present invention to provide a wafer level package for chip scale packaging (CSP) that does not have the drawbacks or shortcomings of the conventional wafer level packages.
It is another object of the present invention to provide a wafer level package by inserting an elastomeric pad into a dummy plug for forming I/O redistribution lines on the package.
It is a further object of the present invention to provide a wafer level package that utilizes an elastomeric pad for stress relieving while eliminating a direct contact of the elastomeric material with a polyimide passivation layer.
It is another further object of the present invention to provide a wafer level package that utilizes elastomeric pads at the bottom of dummy plugs for stress relieving without causing a capacitance problem for the package.
It is still another object of the present invention to provide a wafer level package that utilizes a stress relieving layer formed of a polyamide or a polyamide/elastomer material.
It is yet another object of the present invention to provide a method for fabricating a wafer level package by first forming dummy plugs on top of elastomeric pads and then building solder bumps on top of the dummy plugs such that the elastomeric pads serve the stress relieving function during a subsequent bonding process with the solder bumps.
It is still another further object of the present invention to provide a method for forming a wafer level package by forming via plugs in a layer of stress-relieving material formed of polyimide or polyamide/elastomer mixture.
It is yet another further object of the present invention to provide a method for fabricating a wafer level package by forming solder bumps on I/O redistribution pads on top of dummy plugs and elastomeric pads such that the elastomeric pads absorb bonding stress during a subsequent solder bonding process.
In accordance with the present invention, a wafer level package that utilizes an elastomeric pad in a dummy plug for stress relief of a solder bump built on top of the dummy plug and a method for forming the wafer level package are provided.
In a preferred embodiment, a method for forming a wafer level package can be carried out by the operating steps of first providing a wafer that has a multiplicity of IC dies formed on a top surface, each of the multiplicity of IC dies has a first I/O pad formed in a first insulating layer, forming an insulating pad of an elastic material on the first insulating layer at a location where a second I/O pad is to be formed, sputter depositing a first metal nucleation layer on the top surface of the wafer, coating a layer of a photoresist material of the top surface and patterning openings for via plugs on the first I/O pad and the insulating pad, filling the openings for via plugs with a metal filling the via plugs, removing the layer of photoresist material and etching away the first metal nucleation layer exposed, depositing a second insulating layer on the top surface of the wafer, dry etching away a surface layer of the second insulating layer exposing the via plugs, sputter depositing a metal layer on top of the wafer and defining an I/O redistribution line providing electrical communication between the via plugs, depositing a third insulating layer on top of the I/O redistribution line, defining and exposing an opening for the second I/O pad in the third insulating layer, and forming a solder bump on the second I/O pad over the insulating pad.
In the method for forming a wafer level package, the step of forming a solder bump may further include depositing an under-bump-metallurgy layer on the second I/O pad prior to forming the solder bump. The step of forming a solder bump may further include the steps of depositing an under-bump-metallurgy layer on the second I/O pad, depositing a fourth insulating layer overlying the under-bump-metallurgy layer, filling via holes formed in the fourth insulating layer on the second I/O pad with a solder material forming the solder bump, removing the fourth insulating layer, and reflowing the solder bump into a solder ball.
In the method for forming a wafer level package, the solder bump may be formed in the via hole by a technique of screen printing, stencil printing, electrodeposition, electroless deposition and pick-and-place solder balls. The insulating pad may be formed of an elastomeric material, or formed of an elastic material that has a Young""s modulus of less than 20 MPa. The first I/O pad may be arranged in a peripheral array on the multiplicity of IC dies. The second I/O pad may be arranged in an area array on the multiplicity of IC dies. The insulating pad may be formed by a stencil printing technique. The openings for the via plugs may be formed by a photolithographic method. The first I/O pad and the second I/O pad may be formed of aluminum or copper. The via plugs may be formed of a material selected from the group consisting of aluminum, copper, aluminum alloys and copper alloys. The step of filling the openings for via plugs may be carried out by an electroplating or printing technique. The metal for forming the via plugs completely covers the insulating pad. The second insulating layer may be formed of a material of polyamide, polyamide/elastomer mixture or benzocyclobutene (BCB).
The present invention is further directed to a wafer level package that includes a wafer which has a multiplicity of IC dies formed on a top surface, each of the multiplicity of IC dies has a first I/O pad formed in a first insulating layer, an insulating pad of an elastic material formed on the first insulating layer at a location where a second I/O pad is to be formed, a first metal nucleation layer on top of the first I/O pad and the insulating pad, two via plugs formed in a second insulating layer over the first I/O pad and the insulating pad, respectively, and I/O redistribution line formed of a conductive metal providing electrical communication between the two via plugs, a third insulating layer on top of the I/O redistribution line, an opening in the third insulating layer exposing a second I/O pad on the via plug over the insulating pad, and a solder bump on the second I/O pad over the insulating pad.
In the wafer level package, the solder bump may further include an under-bump-metallurgy layer on the second I/O pad. The insulating pad may be formed of an elastomeric material. The insulating pad may have a diameter of at least 200 nm. The first I/O pad may be arranged in a peripheral array and the second I/O pad may be arranged in an area array. The second insulating layer may be formed of a material of polyimide, polyimide/elastomer mixture or BCB. The via plug under the second I/O pad partially covers the insulating pad.